Title：High Performance 5G-Mobile-SOC/ Computing Chip for edge AI Application Manufactured with 3nm EUV FinFET
Location: Grand Ballroom, 4th Floor, Crowne Plaza Kunming City Centre
Speaker: Dr. Jun Yuan, Senior Director of Engineering，Qualcomm, USA

 

Abstract: We will present the evolution history of Qualcomm cutting edge 5G mobile SOC and computing chip platform (Snapdragon8 flagship) happened in recent years, including the latest Snapdragon8 Gen5 and X-elite chip manufactured with the most advance 3nm process technology – the last FinFET technology before Gate-All-Around (GAA) technology adoption. This high-performance mobile-SOC and computing platform with NPU core also deliver cutting-edge on-device generative AI performance which fuels a more capable, reliable, private & secure path forward in the future.  Their Power-Performance-Area-Cost (PPAC) continuous improvements from node-to-node had been driven by Design Technology co-optimization (DTCO). We will also review those current challenges due to Moore’s law slowing down, and explore the future opportunities including System-Technology Co-Optimization (STCO) to further enhance its PPAC benefits.

 

Bio: 

Dr. Jun Yuan
Senior Director of Engineering，Qualcomm, USA

Dr Jun Yuan is Senior Director of Engineering in Qualcomm Process Technology /Foundry Engineering department in San Diego, USA. He has ~30 years’ experience in Semiconductor field.

Dr Yuan had been Leading multi-generation process technology development (45nm, 28nm, 20nm, 10nm, 8nm, 5nm, 4nm, 3nm) in ramping up multi- Qualcomm premium-tier mobile SOCs into volume production by improving chip Power-Performance-Area-Cost (PPAC). Currently he is leading 3nm process technology for Snapdragon8 Gen4/5 mobile/computing production ramp up, after successfully bringing up snapdragon8 Gen1 & 2 & 3 into production with 4nm technology node.

Prior to joining Qualcomm, he worked as advisory engineer in IBM micro-electronic center developing 45nm/28nm technology (2005-2010), and senior process engineer in Applied Materials (1996-1999).

He received his Ph.D. degree in Electric Engineering Department in University of California, Los Angeles (1999-2005). He has served as IEDM committee member in 2016 & 2017, published >40 technical conference & Journal papers (VLSI, IEDM, IEEE EDL..), and filed >30 patterns.