2021 IEEE 14th International Conference on ASIC

Oct. 26-29, 2021, Kunming, China

Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques



T-1 Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques

Prof. Kenichi Okada
Tokyo Institute of Technology, Japan

In this tutorial, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption especially for low-power applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, an oversampling PLL is introduced for extending the loop bandwidth.


Prof. Kenichi Okada

Kenichi Okada received the B.E., M.E., and Ph.D. degrees in Communications and Computer Engineering from Kyoto University in 1998, 2000, and 2003, respectively. From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. In 2003, he joined Tokyo Institute of Technology where he is now a Professor of Electrical and Electronic Engineering. He was a recipient or co-recipient of the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011 and Best Design Award in 2014 and 2015, the RFIC Symposium Best Student Paper Award in 2019, the Kenjiro Takayanagi Achievement Award in 2020, the IEEE CICC Best Paper Award in 2020. He is/was a member of the technical program committees of IEEE International Solid-State Circuits Conference (ISSCC), VLSI Circuits Symposium, European Solid-State Circuits Conference (ESSCIRC), Radio Frequency Integrated Circuits Symposium (RFIC), and he also is/was Guest Editors and an Associate Editor of IEEE Journal of Solid-State Circuits (JSSC), an Associate Editor of IEEE Transactions on Microwave Theory and Techniques (T-MTT), a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).