ASICON 2019 Tutorial Session
Oct. 29, 2019, Tuesday
Meeting Room: “Xi’an+Dalian”. 4th Fl., Chongqing Hilton Hotel
9:00 - 10:30
T-1 Negative Capacitor Field Effect Transistors (NC-FET)
Speaker:Prof. Muhammad A. Alam, University of Purdue, USA

Abstract:Negative Capacitor Field Effect Transistors (NC-FET) promises to sustain Moore’s law by reducing the supply voltage (and thereby, self-heating) below the lowest limit achievable by classical transistors. Conceptually, the reduction is supply voltage is achieved by integrating a negative capacitor in the gate-stack; the internal voltage amplification turns a transistor on and off at voltages much lower that previously presumed possible. Unfortunately, the notion of a ‘negative capacitor’, the debate regarding experimental demonstrations, apparent disconnect with equations of classical transistors, etc. make NC-FET a mysterious and hard-to-understand addition to device literature. In this talk, I use a simple graphical approach to demystify the device and explain why the experimental results are easy to misinterpret. Since NC-FET is just a special case of a much broader range of phase-change devices and systems (e.g., transistors, memories, MEMS, logic-in-memory architecture) that operate by tailoring the Landau potential energy landscape, therefore, once NC-FET is understood, the operation of all other devices would become intuitively obvious as well.

Bio:Professor Alam is the Jai N. Gupta Professor of Electrical Engineering at Purdue University, where his research focuses fundamental limits of classical- (transistors and solar cells) and emerging- (biosensors, flexible electronics) electronic devices. Before joining Purdue in 2004, Prof. Alam spend a decade in Bell Labs and Agere systems where he made important contributions to reliability physics of transistors and design of optoelectonic ICs. He has published more than 250 papers, presented numerous invited and contributed talks, and more than 300,000 students have learned some aspect of the semiconductor devices from his web-enabled courses. He is a fellow of IEEE, APS, and AAAS, and the recipient of 2006 IEEE Kiyo Tomiyasu Award, 2015 SRC Technical Excellence Award, and 2018 IEEE EDS Education Award, all for fundamental contributions to device technology for communication systems.

10:45 – 12:15
T-2 Single-Bit Delta-Sigma Modulation Techniques for Robust Communication Systems
Speaker :Prof. Woogeun Rhee, Tsinghua University, China

Abstract: As future communication systems demand not only low-power but also low-voltage design with advanced CMOS technology, matching and linearity problems in analog/RF circuits have become more critical than ever. The  modulation technique enables robust mixed-signal design but still requires careful design over nonlinearity when a multi-bit  quantizer is used. This talk discusses an extensive use of a 1-bit  modulation method to build robust communication systems by mitigating the nonlinearity problem. In this talk, four examples of modulation and transceiver systems which utilize the 1-bit modulation/conversion schemes are introduced, including two-point modulation without DCO nonlinearity calibration, SSCG/FMCW modulation based on the BBPLL, and phase-domain receivers with 1-bit noise-shaping demodulation, and time-of-flight (TOF) ranging transceivers with a 1-bit  TDC.
Bio: Woogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001.
From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and developed low-power, low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking area for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty as an Associate Professor at the Institute of Microelectronics, Tsinghua University, Beijing, China, and became a Professor in December 2011. His current research interests include short-range low-power radios for next generation wireless systems and clock/frequency generation circuits for wireline and wireless communications. He holds 23 U.S. patents.
Dr. Rhee is an IEEE Distinguished Lecturer of the Solid-State Circuits Society (2016-2017) and served as an Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS (2012-2018). He has been an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART-II: EXPRESS BRIEFS (2008-2009) and a Guest Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in November 2012 and November 2013. He has served as a member of several IEEE conferences, including ISSCC (2012-2016), CICC, and A-SSCC.

14:00 – 15:30
T-3 Radiation Hardening by Design of Digital Circuits
Speaker: Prof. Kazutoshi Kobayashi, Kyoto Institute of Technology, Japan

Abstract: Single events by alpha particles and neutrons on the terrestrial region threaten safety, reliability and serviceability of semiconductor devices on which our daily life highly depends on Radiation hardening by design must be taken into account for mission critical applications such as autonomous driving, aerospace and so on. This tutorial will provide an introduction of single events on digital circuits to cause a single event upset (SEU) on storage cells such as SRAMs, latches and flip-flops. Then several radiation hardening-by-design (RHBD) techniques will be introduced to mitigate SEU including multimodular structures applicable to both of bulk and SOI and stacking structures effective to SOI.
Despite significant progress made in recent years, in particular with the introduction of FinFET transistors into the high-volume manufacturing market, radiation-induced soft error reliability remains one of the most important fundamental issues in silicon technology. This tutorial will provide an introduction into all key topics to get you prepared for embarking into soft errors and for quickly becoming a productive contributor. Covered topics include: SE mechanism overview, testing for SE, modeling, trends and mitigation
Bio: Kazutoshi Kobayashi received his BE,ME and Ph.D in Electronic Engineering from Kyoto University, Japan in 1991,1993,1999, respectively. Starting as an Assistant Professor in 1993, he was promoted to associate professor in the Graduate School of informatics, Kyoto University, and stayed in that position until 2009. For two years during this time, he acted as associate professor of VLSI Design and Education Center (VDEC) at the University of Tokyo. Since 2009, he has been a professor at Kyoto Institute of Technology.
While in the past he focused on reconfigurable architectures utilizing device variations, his current research interest in in improving the reliability (Soft Errors, Bias Temperature Instability and Plasma Induced Damage) of current and future VLSIs. He started a research related to gate drivers for power transistors since 2013.
He was the recipient of the IEICE best paper award in 2009 and the IRPS best poster award in 2013.

15:45 – 17:15
T-4 Low Power Smart Sensor Node Processor design
Speaker: Prof. Jun Zhou, UESTC, China

Abstract : Smart sensing has been widely adopted in applications including health monitoring, intelligent surveillance and smart robots. There are several common requirements for the smart sensing applications, including intelligence, real-time processing, low power consumption and miniaturization. Among them, the requirements for intelligence, real-time processing and miniaturization pose big challenge on the requirement of low power consumption. This tutorial talks about how to address the abovementioned challenge by combining innovation and optimization through the design hierarchy on algorithm, architecture and circuit levels in the design of smart sensor node processor.

Bio: Professor of National Thousand Youth Talents Scheme, Head of IoT Smart ICs & Systems Group, University of Electronic Science and Technology of China. His major research interests include algorithm & processor co-design for smart sensing applications and low power digital IC design. He has published more than 60 papers in prestigious conferences and journals including ISSCC, JSSC, DAC, TCAS-I, TVLSI, ESSCIRC and A-SSCC. His work has been reported by EE Times and has received the IEEE Circuits & Systems Society Seoul Chapter Award. He is currently an IEEE senior member, the Associate Editor of IEEE Transactions on Very Large Scale Integration System (TVLSI), the Chair of A-SSCC Digital Circuits & Systems Sub-Committee and the Chair of Embedded AI Committee of Sichuan Institute of Electronics. He is also OC/TPC member of a number of prestigious IEEE conferences including ICCD, ISCAS, SOCC and DSP.

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